\chapter{Introduction}
This document is describes and specifies the various different parts of the ELB816 development system. Interfaces between the various subsystems are defined and specifications for the internal operations of the sub-systems are outlined.
An overview of the whole system structure is shown in \reffig{fig:int_overview} on \refpage{fig:int_overview}.  For the purposes of this document we will assume that the host computer system will be an IBM PC compatible running Windows or Linux but support for Apple Mac and other systems will be realised if a platform independent language such as Java or Python is used. To disambiguate terms, for the rest of this document, the term `PC' will be used to refer to the `Program Counter' register of the target processor. 
The elements in the `Host software' section are as follows: 

\begin{itemize}
\item The main GUI provides an intuitive user interface for the user to control the system.

\item The editor allows assembly code files to be created and edited and will implement automatic colour mark up of code to facilitate easy reading.

\item The assembler translates assembly language text files into binary machine code files which may be run on the ELB816 processor.

\item The debugger controls the target processor system and allows code to be downloaded, tested and debugged easily. Initially, there will be three possible targets: a software emulator, a hardware emulator running in an MCS-51 compatible MCU and a full hardware implementation of the ELB816 running in an FPGA. The debugger only talks to one specific target at any one time but may switch between them at the user's command.

\item Target 1 is a software emulation of the processor system which is implemented in the host software itself. This emulator allows users to test their programs without the need of hardware boards. The software emulator processor system also requires emulated peripheral I/O devices such as interrupt controllers, serial and parallel ports plus keypads and displays. The software hierarchy for this mode of operation is shown in Figure 2.

\item The host serial interface (target 2) presents a second target interface to the debugger allowing communication with target processor systems that have been implemented in hardware via a serial port (or via USB emulated serial port).
The MCU system can either implement a hardware emulation of the processor (target 2a) or simply serve as a communication link for a full hardware implementation on an FPGA (target 2b).
\end{itemize}

\begin{figure}
 \centerline{
 \includegraphics[height=0.9\textheight]{../images/eps/system_overview.eps}}
 \caption{ELB816 Development system overview}
 \label{fig:int_overview}
\end{figure}

\begin{figure}
 \centerline{
 \includegraphics[height=0.15\textheight]{../images/eps/target1.eps}}
 \caption{Target 1 software hierarchy - using the software emulator as a target}
 \label{fig:int_target1}
\end{figure}

\begin{figure}
 \centerline{
 \includegraphics[height=0.2\textheight]{../images/eps/target2.eps}}
 \caption{Target 2a software hierarchy - MCU hardware emulator}
 \label{fig:int_target2}
\end{figure}

\begin{figure}
 \centerline{
 \includegraphics[height=0.3\textheight]{../images/eps/target3.eps}}
 \caption{Target 2b software hierarchy - processor implemented in FPGA hardware}
 \label{fig:int_target3}
\end{figure}

When used with a hardware emulated system on the MCU, some peripherals may need to be emulated in the MCU software (such as interrupt controllers) but others may just require drivers for real I/O devices externally connected to the MCU.  The software hierarchy for this mode of operation is shown in Figure 3 on page 5.
When used with the FPGA implementation, the MCU serial interface will communicate with an FPGA hardware driver layer to control the hardware target processor.  The software hierarchy for this mode of operation is shown in Figure 4 on page 5.
